CPUID model numbers are 02h (earliest "Vishera" Piledrivers) and 10h-1Fh. AMD Piledriver Family 15h (2nd-gen) – second generation Bulldozer (First optimisation).For Bulldozer, CPUID model numbers are 00h and 01h. Orochi was the first design which implemented it. Bulldozer is designed for processors in the 10 to 220 W category, implementing XOP, FMA4 and CVT16 instruction sets. AMD Bulldozer Family 15h – the successor to 10h/K10.AMD Puma Family 16h (2nd-gen) – the successor to Jaguar.AMD Jaguar Family 16h – the successor to Bobcat.Ontario and Zacate were the first designs which implemented it. AMD Bobcat Family 14h – a new distinct line, which is aimed in the 1 W to 10 W low power microprocessor category.Llano was the first design which implemented it. Includes CPU cores, GPU and Northbridge in the same chip. AMD Fusion Family 12h – based on the 10h/K10 design.AMD Family 11h – combined elements of K8 and K10 designs for Turion X2 Ultra / Puma mobile platform.Barcelona was the first design which implemented it. Shared Level 3 Cache, 128-bit floating point units, AMD-V Nested Paging virtualization, and HyperTransport 3.0 are introduced. AMD Family 10h (K10) – based on the K8 microarchitecture.The codename was recycled at least once until ultimately being dropped before any public mention of it. SledgeHammer was the first design which implemented it. K8 replaced the traditional front side bus with a HyperTransport communication fabric. The K8 was the first mainstream Windows-compatible 64-bit microprocessor and was released April 22, 2003. Based on the K7 but was designed around a 64-bit ISA, added an integrated memory controller, HyperTransport communication fabric, L2 cache sizes up to 1 MB (1128 KB total cache), and SSE2. AMD K8 Hammer – also known as AMD Family 0Fh.
#Amd k10 architecture full
The third generation, branded as XP, introduced full support for SSE. The second generation returned to the traditional socket form factor with fully integrated L2-cache running at full speed.
First generation was built with a separate L2-cache chip on a board inserted into a slot ( A) and introduced extended MMX.
#Amd k10 architecture code
(The "K10h" form that sometimes pops up is an improper hybrid of the "K" code and Family XXh identifier number.) Family numberīulldozer / Piledriver / Steamroller / Excavator In hexadecimal numbering, 0F(h) (where the h represents hexadecimal numbering) equals the decimal number 15, and 10(h) equals the decimal number 16. 10h and 0Fh refer to the main result of the CPUID x86 processor instruction. AMD now refers to the codename K8 processors as the Family 0Fh processors. AMD has not used K-nomenclature codenames in official AMD documents and press releases since the beginning of 2005, when K8 described the Athlon 64 processor family. Historically, AMD's CPU families were given a "K-number" (which originally stood for Kryptonite, an allusion to the Superman comic book character's fatal weakness) starting with their first internal x86 CPU design, the K5, to represent generational changes. The following is a list of AMD CPU microarchitectures.